VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
(1,0)
VMLOCK (Output)
VMA27 to VMA0 (Output)
A.0
VMWRITE (Output)
VMBENZ3 to VMBENZ0 (Output)
(1,1,0,0)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
(0,1,1)
VMSIZE1, VMSIZE0 (Output)
VMSTZ (Output)
VMBSTR (Output)
L
VBDC (Output)
VBDV (Output)
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output)
H
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output)
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Word transfer
Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (6/12)
(f) 16-bit bus (4-word sequential transfer, data access)
Read
(1,1)
A.1
A.2
A.3
A.4
A.5
A.6
(1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0)
(0,0,1)
(0,0,1)
(1,0)
xxH
D.0
D.1
D.2
D.3
D.4
D.5
Word transfer
Word transfer
Word transfer
Idle
(0,0)
(1,0)
A.7
A.8
A.9
(1,1,1,1)
(1,1,0,0)
(1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0) (1,1,0,0)
(0,0,0)
(0,1,1)
FFH
D.6
D.7
D.8
D.9
Word transfer
Write
(1,1)
A.10
A.11
A.12
A.13
A.14
A.15
(0,0,1)
(0,0,1)
(0,0,0)
(1,0)
xxH
D.10
D.11
D.12
D.13
D.14
D.15
Word transfer
Word transfer
Word transfer
Idle
(0,0)
(1,1,1,1)
FFH