Precautions - Renesas NU85E Preliminary User's Manual

7.15 Precautions

(1) Memory boundary
Operation is not guaranteed if the address of the transfer source or transfer destination is outside of the area for
the DMA object (external memory, RAM, or peripheral macro) during a DMA transfer.
(2) Misalign data transfer
DMA transfer of misalign data with a 32-bit or 16-bit bus width is not supported.
(3) Intervals related to DMA transfer
The overhead before a DMA transfer and the minimum number of clocks required for a DMA transfer are shown
below.
• From the acknowledgement of the DMARQn signal until the rising edge of the DMACTVn signal (n = 3 to 0):
3 clocks
• From when the DMARQn signal is acknowledged until the rising edge of the IRAMEN signal for transfer from
RAM to VSB (n = 3 to 0): 3.5 clocks
• Access to RAM connected to VDB: 1 clock
In the case of external memory access, these depend on the connected MEMC and the external memory. An
example is shown below.
Example When SRAM is accessed using the MEMC (NT85E500)
Transfer
Type
Two-cycle • Time between start of read cycle and end of write cycle
• The transfer time of one transfer for single and single-step transfers,
and four transfers for a line transfer.
• The combinations of transfer sources and destinations are as follows.
<Transfer source> <Transfer destination>
VSB
VSB
RAM
RAM
Time in which bus is released to CPU
Flyby Transfer time of one transfer from SRAM to I/O, and from I/O to SRAM
204
CHAPTER 7 DMAC
Conditions
→
VSB
→
RAM
→
VSB
→
RAM
Preliminary User's Manual A14874EJ3V0UM
Transfer Minimum
Mode Clock Number
Single 5 clocks
Single-step 5 clocks
Line 32 clocks
Single 6 clocks
Single-step 4 clocks
Line 6 clocks
−
3 clocks