Forcible Termination; Dma Transfer Forcible Termination Example - Renesas NU85E Preliminary User's Manual

7.13 Forcible Termination

By setting (1) the INITn bit of the DCHCn register during a DMA transfer, it is possible to forcibly terminate the
DMA transfer under execution. The following is an example of the operation of a forcible termination (n = 0 to 3).
Caution The setting (1) of the INITn bit is performed when the VSB has been released to the CPU (n = 0 to
3). Therefore, because the VSB is locked until the DMA transfer has completely finished in a
block transfer using the VSB, it is not possible to exercise a forcible termination during this
transfer.
Figure 7-29. DMA Transfer Forcible Termination Example (1/2)
(a) Block transfer using DMA channel 3 begins during block transfer using DMA channel 2
DSA2, DDA2, DBC2,
DADC2, DCHC2
DMARQ2
(Input)
EN2 bit = 1
TC2 bit = 0
DMARQ3
(Input)
CPU CPU
178
CHAPTER 7 DMAC
Set register
DSA3, DDA3, DBC3,
DADC3, DCHC3
Set register
EN3 bit = 1
TC3 bit = 0
CPU CPU DMA2 DMA2 DMA2
Preliminary User's Manual A14874EJ3V0UM
DCHC2
(INIT2 bit = 1)
Set register
EN2 bit → 0
TC2 bit = 0
DMA2 DMA2 CPU DMA3 DMA3
DMA channel 3 transfer begins
DMA channel 2 transfer is forcibly terminated
and the bus is released
EN3 bit → 0
TC3 bit → 1
DMA3 DMA3 CPU CPU
DMA channel 3 terminal count
CPU