Debug Function - Renesas NU85E Preliminary User's Manual

10.3 Debug Function

(1) Debug interface
Communication with the host machine is performed via the N-Wire type IE using the DCK, DRSTZ, DMS, DDI,
and DDO signals. JTAG communication specification is used for the interface. The boundary scan function is
not supported.
(2) On-chip debug
By connecting with the N-Wire type IE, it is possible to debug the NB85E901 on the NU85E chip.
For details on the above connection, refer to 10.5 N-Wire Type IE Connection.
(3) Forcible reset function
The NB85E901 unit can be forcibly reset.
(4) Break reset function
The CPU can be started in debug mode immediately after CPU reset release.
(5) Forcible break function
Execution of the user program can be forcibly interrupted. Note that the illegal opcode exception handler (start
address: 00000060H) cannot be used.
(6) Debug interrupt interface
The forcible break function can be executed by inputting a high level to the DBINT pin.
Remark It is also possible to release the HALT, software STOP, and hardware STOP modes by DBINT input.
(7) Breakpoint function
Execution of the user program can be interrupted at an arbitrary address. Also, data access to an arbitrary
address can be interrupted. Note that the illegal opcode exception handler (start address: 00000060H) cannot
be used.
There are two kinds of instruction/access alternate breakpoints: a pre-execution break and a post-access
execution break.
(8) Debug monitor function
A debug-dedicated memory space, which is different to the user memory space, is used during debugging
(background monitor format). Execution of the user program can be started from an arbitrary address.
It is also possible to read/write the user resource (such as memory and I/O) and download the user program
during a user program interruption.
(9) Mask function
The external input signals (RESETZ, STOPZ, NMI2 to NMI0, VAREQ, WAITZ) can be masked.
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CHAPTER 10 NB85E901
Preliminary User's Manual A14874EJ3V0UM