Example Of Two-Cycle Line Transfer Timing (Between External Srams Connected To Nt85E500) - Renesas NU85E Preliminary User's Manual

Figure 7-32. Example of Two-Cycle Line Transfer Timing (Between External SRAMs Connected to NT85E500)
1st
VBCLK (Input)
VMTTYP1, VMTTYP0
0H 2H 2H 3H 0H
(Output)
VMA27 to VMA0 (Output)
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output)
VMSTZ (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0
FH 0H FH
(Output)
VMCTYP2 to VMCTYP0
6H
(Output)
VMSEQ2 to VMSEQ0
0H
(Output)
VMSIZE1, VMSIZE0
2H
(Output)
VMLOCK (Output)
VBDC (Output)
VBDV (Output)
VDCSZ7 to VDCSZ0
FFH FBH FFH
(Output)
VMWAIT (Input)
VMAHLD (Input) L
VMLAST (Input) L
DMARQn (Input)
DMACTVn (Output)
DMTCOn (Output) L
A25 to A0 (Output) Note
DI31 to DI0 (Input) Note
DO31 to DO0 (Output) Note
RDZ (Output) Note
WRZ3 to WRZ0 (Output) Note
FH
CSZ7 to CSZ0 (Output) Note
FFH FBH FFH
Note These are NT85E500 signals.
2-cycle line transfer
2nd
2H 3H 0H 2H 3H 0H 2H 3H
0H FH 0H FH 0H
6H 6H 6H
0H 0H 0H
2H 2H 2H
FBH FFH FBH FFH FBH
0H FH 0H
FBH FFH FBH FFH FBH
3rd
0H 2H 3H 0H 2H 3H 0H 2H
FH 0H FH 0H FH 0H
6H 6H 6H
0H 0H 0H
2H 2H 2H
FFH FBH FFH FBH FFH FBH
FH 0H FH
FFH FBH FFH FBH FFH FBH
CPU cycle
4th
5th
3H 0H 2H 3H 0H 2H 3H 0H
FH 0H FH 0H FH
6H 6H
0H 0H
2H 2H
FFH FBH FFH FBH FFH
0H FH
FFH FBH FFH FBH FFH
Next line transfer
2H 3H 0H
0H FH
6H
0H
2H
FBH FFH
0H FH
FBH FFH