Renesas NU85EA Manuals

Manuals and User Guides for Renesas NU85EA. We have 1 Renesas NU85EA manual available for free PDF download: Preliminary User's Manual

Renesas NU85EA Preliminary User's Manual

Renesas NU85EA Preliminary User's Manual (257 pages)

32-Bit Microprocessor Core

Brand: Renesas | Category: Computer Hardware | Size: 1.93 MB

Table of Contents

Table of Contents
11
Chapter 1 Introduction

19
- Outline
  19
- Application System Example
  20
- Features
  21
- Symbol Diagram
  23
- Function Blocks
  24
- Internal Block Diagram
  24
- Internal Units
  25
- Functional Differences between NU85E and NB85E
  26
Chapter 2 Pin Functions

27
- List of Pin Functions
  27
- Explanation of Pin Functions
  31
- NPB Pins
  31
- VSB Pins
  32
- System Control Pins
  36
- Acknowledgement of DCRESZ Signal
  36
- Stopping VBCLK Oscillation by System Reset
  37
- DMAC Pins
  38
- INTC Pins
  38
- VFB Pins
  38
- VDB Pins
  39
- Instruction Cache Pins
  40
- Data Cache Pins
  41
- RCU Pins
  43
- Peripheral Evaluation Chip Mode Pins
  43
- Operation Mode Setting Pins
  44
- Test Mode Pins
  46
- Recommended Connection of Unused Pins
  48
- Pin Status
  50
Chapter 3 Cpu

53
- Features
  53
- Registers
  54
- List of CPU Registers
  54
- Program Registers
  55
- Program Counter (PC)
  56
- System Registers
  57
- Interrupt Source Register (ECR)
  58
- Program Status Word (PSW)
  59
- Address Space
  60
- Program Area
  61
- Data Area
  62
- Data Area (64 MB Mode)
  62
- Data Area (256 MB Mode)
  63
- Areas
  64
- ROM Area
  64
- RAM Area
  66
- Peripheral I/O Area
  67
- Peripheral I/O Area
  68
- External Memory Area
  69
- Peripheral I/O Registers
  69
- NU85E Control Registers
  70
- Memory Controller (MEMC) Control Registers
  73
- Instruction Cache Control Registers
  74
- Data Cache Control Registers
  74
- RCU Interface
  75
- Outline
  75
- On-Chip Debugging
  75
- Connection of NU85E and N-Wire Type In-Circuit Emulator Via RCU
  75
Chapter 4 Bcu

76
Chapter 5 Bbr

120
- NPB Connection Overview
  120
- NU85E and Peripheral Macro Connection Example
  121
- Programmable Peripheral I/O Area
  122
- Peripheral I/O Area and Programmable Peripheral I/O Area
  122
- Peripheral I/O Area Select Control Register (BPC)
  123
- BPC Register Setting Example
  124
- Wait Insertion Function
  125
- NPB Strobe Wait Control Register (VSWC)
  125
- Retry Function
  127
- NPB Read/Write Timing
  128
- Halfword Access Timing
  128
- Timing of Byte Access to Odd Address
  129
- Timing of Byte Access to Even Address
  129
- Read Modify Write Timing
  130
- Retry Timing (Write)
  130
- Retry Timing (Read)
  131
- Read/Write Timing of Bus Slave Connected to NPB
  132
- NPB Write Timing (Example of Timing of Data Write to CSC0 and CSC1 Registers)
  136
- Precautions
  137
Chapter 6 Stbc

138
- Power Save Function
  138
- Power Save Function State Transition Diagram
  138
- Control Registers
  139
- Power Save Control Register (PSC)
  139
- Command Register (PRCMD)
  141
- HALT Mode
  142
- Software STOP Mode
  143
- Hardware STOP Mode
  145
- Clock Control in Software/Hardware STOP Mode
  146
- Connection of NU85E and Clock Control Circuit
  146
- Software STOP Mode Set/Cancel Timing Example
  148
- Hardware STOP Mode Set/Cancel Timing Example
  150
Chapter 7 Dmac

151
Chapter 8 Intc

208
- Features
  208
- Non-Maskable Interrupts (NMI)
  211
- Example of Non-Maskable Interrupt Request Acknowledgement Operation
  212
- Operation
  214
- Non-Maskable Interrupt Processing Format
  214
- Restore
  215
- RETI Instruction Processing Format
  215
- Maskable Interrupts
  216
- Operation
  216
- Maskable Interrupt Processing Format
  217
- Restore
  218
- RETI Instruction Processing Format
  218
- Maskable Interrupt Priorities
  219
- Servicing Example in Which Another Interrupt Request Is Issued During Interrupt Servicing
  220
- Servicing Example for Simultaneously Issued Interrupt Requests
  222
- Control Registers
  223
- Interrupt Control Registers 0 to 63 (PIC0 to PIC63)
  223
- Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
  224
- In-Service Priority Register (ISPR)
  225
- Maskable Interrupt Status Flag (ID)
  226
- Program Status Word (PSW)
  226
- Software Exception
  227
- Operation
  227
- Software Exception Processing Format
  227
- Restore
  228
- RETI Instruction Processing Format
  228
- Exception Trap
  229
- Illegal Opcode
  229
- Operation
  230
- Restore
  230
- Exception Trap Processing Format
  230
- Interrupt Response Time
  231
- Periods When Interrupts Cannot be Acknowledged
  231
- Example of Pipeline Operation When Interrupt Request Is Acknowledged (Outline)
  231
Chapter 9 Test Function

232
- Test Pins
  232
- Test Bus Pins (TBI39 to TBI0 and TBO34 to TBO0)
  232
- BUNRI and TEST Pins
  232
- BUNRIOUT Pin
  233
- List of Test Interface Signals
  233
- Example of Connection of Peripheral Macro in Test Mode
  234
- Peripheral Macro Connection Example
  234
- Handling of each Pin in Test Mode
  235
Chapter 10 Nb85E901

236
- Symbol Diagram
  236
- Pin Functions
  237
- Pin Function List
  237
- Pin Functions
  238
- Recommended Connection of Unused Pins
  241
- Pin Status
  242
- Debug Function
  244
- NU85E Connection Example
  245
- NB85E901 and NU85E Connection Example
  245
- N-Wire Type IE Connection
  246
- IE Connector (Target System Side)
  246
- IE Connector Pin Layout Diagram (Target System Side)
  246
- Example of Recommended Circuit When Connecting NB85E901 and NU85E
  248
- Example of Recommended Circuit for IE Connection (NU85E + NB85E901)
  248
Appendix A Rom/Ram Access Timing

249
- ROM Access Timing
  249
- RAM Access Timing
  250
Appendix B Index

251
Appendix C Revision History

256

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