One-Time Transfer When Executing Single Transfers Using Dmarqn Signal; One-Time Transfer When Executing Single Transfers Using Dmarqn Signal - Renesas NU85E Preliminary User's Manual

7.8.5 One-time transfer when executing single transfers using DMARQn signal

(1) Two-cycle transfer
When executing single transfers to the external memory using the DMARQn signal input, the next DMARQn
signal is acknowledged when its sampling is started at the rise of VBCLK three clocks following the completion of
the write cycle of the current 2-cycle transfer. Actually, when the specified DMARQn setup time is satisfied after
VBCLK falls 2.5 clocks after completion of the write cycle, the next DMARQn signal request is acknowledged.
Therefore, in order to transfer only once, it is recommended that the DMARQn signal be made inactive within 2
clocks of the end of the write cycle of a 2-cycle single transfer (n = 3 to 0).
During a DMA transfer in which the destination is the RAM connected to the VDB, the DMACTVn signal does not
become active during transfer to RAM, so if the transfer destination (write cycle) is RAM, the timing when the
write cycle ends cannot be determined (n = 3 to 0). When executing a single transfer, whether from memory to
RAM or from RAM to memory, the DMACTVn signal becomes active during the memory transfer. In this case,
therefore, it is recommended that the DMARQn signal be made inactive within 2 clocks after the DMACTVn
signal becomes inactive.
Figure 7-23. One-Time Transfer When Executing Single Transfers Using DMARQn Signal
VBCLK (Input)
VMTTYP1, VMTTYP0
(0,0)
(Output)
VMA27 to VMA0 (Output)
VMSTZ (Output)
VMWRITE (Output)
VBDC (Output)
VBDV (Output)
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output)
VMWAIT (Input)
DMARQn (Input)
DMACTVn (Output)
Remark O mark: Sampling timing
A.x: Arbitrary address output from the VMA27 to VMA0 pins
D.x: I/O data for address "A.x"
: Arbitrary input level
n = 3 to 0
172
CHAPTER 7 DMAC
2-cycle single transfer
Read cycle
(1,0) (1,1) (0,0)
A.0
D.0
Preliminary User's Manual A14874EJ3V0UM
Write cycle
(1,0) (1,1)
A.1
D.1
The DMARQn signal must be
inactive by this point
(0,0)
Sampling DMARQn
signal started