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Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (4/12)
(d) 32-bit bus (single transfer, 2 waits inserted, with address hold)
VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
(1,0)
VMLOCK (Output)
L
VMA27 to VMA0 (Output)
A.0
VMWRITE (Output)
L
VMBENZ3 to VMBENZ0 (Output)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
VMSIZE1, VMSIZE0 (Output)
VMSTZ (Output)
VMBSTR (Output)
L
VBDC (Output)
VBDV (Output) L
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output)
H
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output) L
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Read
(1,1)
(1,0)
(1,1)
(1,0)
A.1
A.2
(0,0,0,0)
(0,0,1)
(0,0,0)
(1,0)
xxH
D.0
D.1
Idle
(1,1)
(0,0)
(1,1,1,1)
FFH
D.2
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