Bus Master Transition - Renesas NU85E Preliminary User's Manual

4.9.6 Bus master transition

There are five kinds of external bus cycles as shown below. Bus hold has the highest priority, followed by refresh
cycle, DMA cycle, operand data access, and instruction fetch in that order.
Priority
High
↑
↓
Low
The bus master transition procedure from master device (M1) which is operating as bus master to other master
device (M2) is as follows.
<1> M1, which operates as the bus master inputs a VSB access right request signal (VAREQ) from M2, another
master device.
<2> The bus arbiter within M1 goes into waiting for the ready response from the bus slave.
<3> Upon completion of the current transfer, the bus slave returns a ready response.
<4> The VMTTYP1 and VMTTYP0 signals of M1 indicate address-only transfer, and the VMLOCK, VDCSZ7 to
VDCSZ0, and VDSELPZ signals are all ignored.
<5> M1 returns an acknowledge signal (VAACK) for the VAREQ signal and a ready response to M2.
<6> M2 becomes the bus master and data transfer on VSB starts.
Remark The ready response is when the VMWAIT, VMAHLD, and VMLAST signals are all in a low-level state.
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CHAPTER 4 BCU
External Bus Cycle
Bus hold
Refresh cycle
DMA cycle
Operand data access
Instruction fetch
Preliminary User's Manual A14874EJ3V0UM
Bus Master
External device
SDRAM controller
DMA controller
CPU
CPU