Single-Step Transfer Mode; Single-Step Transfer Example 1; Single-Step Transfer Example 2 - Renesas NU85E Preliminary User's Manual

7.8.2 Single-step transfer mode

In single-step transfer mode, the DMAC releases the bus after each byte, halfword, or word transfer. Once a DMA
transfer request signal (DMARQ3 to DMARQ0) is received, this operation continues until a terminal count occurs.
If a higher priority DMA transfer request is generated while the DMAC has released the bus, the higher priority
DMA transfer request always takes precedence.
Figures 7-16 and 7-17 show single-step transfer mode examples.
DMARQ1
(Input)
CPU CPU
Note The bus is always released.
DMARQ0
(Input)
DMARQ1
(Input)
CPU CPU
Note The bus is always released.
168
CHAPTER 7 DMAC
Figure 7-16. Single-Step Transfer Example 1
Note Note
CPU DMA1 CPU DMA1 CPU
Figure 7-17. Single-Step Transfer Example 2
Note Note
CPU DMA1 CPU DMA1 CPU
Preliminary User's Manual A14874EJ3V0UM
Note
DMA1 CPU DMA1 CPU CPU
DMA channel 1 terminal count
Note Note
DMA0 CPU DMA0 CPU DMA0
DMA channel 0
terminal count
CPU CPU CPU CPU CPU
Note Note
CPU DMA1 CPU DMA1 CPU
DMA channel 1
terminal count