Ram Access Timing - Renesas NU85E Preliminary User's Manual

VBCLK (Input)
IRAMRWB (Output)
IRAMEN (Output)
IRAMA27 to IRAMA2
(Output)
IRAMZ31 to IRAMZ0
(Input)
Remarks 1. Ax: Arbitrary address
Dx: Data corresponding to address "Ax"
2. : RAM data sampling timing
VBCLK (Input)
IRAMRWB (Output)
IRAMEN (Output)
IRAMA27 to IRAMA2
(Output)
IRAMWR3 to IRAMWR0
(Output)
IRAOZ31 to IRAOZ0
(Output)
Remark Ax: Arbitrary address
Dx: Data corresponding to address "Ax"
248
APPENDIX A ROM/RAM ACCESS TIMING
Figure A-2. RAM Access Timing
(a) Read timing
A0
D0
(b) Write timing
A0
WE0
D0
Preliminary User's Manual A14874EJ3V0UM
A1 A2
D1 D2
A1 A2
WE1 WE2
D1 D2