Renesas NU85E Preliminary User's Manual page 160

Figure 7-6. DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) (2/2)
Bit position Bit name
7, 6 SAD1,
SAD0
5, 4 DAD1,
DAD0
3, 2 TM1,
TM0
1 TTYP
0 TDIR
Remark n = 0 to 3
Note Valid only when using the MEMC associated with the flyby transfer.
158
CHAPTER 7 DMAC
Sets the count direction of the transfer source addresses for DMA channels n (n = 0 to 3).
SAD1 SAD0
0 0 Increment
0 1 Decrement
1 0 Fixed
1 1 Setting prohibited
Sets the count direction of the transfer destination addresses for DMA channels n (n = 0 to 3).
DAD1 DAD0
0 0 Increment
0 1 Decrement
1 0 Fixed
1 1 Setting prohibited
Sets the transfer mode used for DMA transfers.
TM1 TM0
0 0 Single transfer mode
0 1 Single-step transfer mode
1 0 Line transfer mode
1 1 Block transfer mode
Sets the DMA transfer type.
0: Two-cycle transfer
Note
1: Flyby transfer
Sets the transfer direction used for transfers between peripheral macros and external memory.
The setting is valid only for flyby transfers and is ignored for 2-cycle transfers.
0: External memory to peripheral macro (read)
1: Peripheral macro to external memory (write)
Preliminary User's Manual A14874EJ3V0UM
Function
Count direction
Count direction
Transfer mode