Peripheral I/O Area Select Control Register (Bpc) - Renesas NU85E Preliminary User's Manual

Figure 5-4. Peripheral I/O Area Select Control Register (BPC)
15 14 13 12
PA PA PA
BPC 0
15 13 12
Bit position Bit name
15 PA15 Sets whether or not the programmable peripheral I/O area can be accessed.
0: It cannot be accessed
1: It can be accessed
13 to 0 PA13 to Specifies bit 27 to bit 14 of the starting address of the programmable peripheral I/O area. (The
PA00 other bits are fixed at zero.)
Caution Always set bit 14 to 0. If it is set to 1, operation is not guaranteed.
Cautions 1. In 64 MB mode, if the programmable peripheral I/O area overlaps the following areas, the
programmable peripheral I/O area becomes ineffective.
• • • • Peripheral I/O area
• • • • ROM area
• • • • RAM area
2. In 256 MB mode, if the programmable peripheral I/O area overlaps the following areas, the
programmable peripheral I/O area becomes ineffective.
• • • • Peripheral I/O area
• • • • ROM area
• • • • RAM area
• • • • The area that is the same as the RAM area and that is located at address 3FFEFFFH and
below (See Figure 3-8 Data Area (256 MB Mode))
3. If no peripheral macros are connected to the NPB, no programmable peripheral I/O area
need be set (Set the BPC register to its after-reset value).
4. The programmable peripheral I/O area address setting is enabled only once. Do not change
addresses in the middle of a program.
Figure 5-5 shows a BPC register setting example and the memory map after the setting is made.
CHAPTER 5 BBR
11 10 9 8 7 6
PA PA PA PA PA PA
11 10 09 08 07 06
Preliminary User's Manual A14874EJ3V0UM
5 4 3 2 1 0
PA PA PA PA PA PA
05 04 03 02 01 00
Function
Address After reset
FFFFF064H 0000H
121