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Bit position
Bit name
2 to 0
VSWL2 to
VSWL0
VBCLK (Input)
VPSTB (Output)
VPA13 to VPA0 (Output)
Be sure to set values for the setup wait and VPSTB wait lengths at each operation frequency that are the same as
or greater than the number of waits shown in Table 5-1 below.
Table 5-1. Setting of Setup Wait, VPSTB Wait Lengths at Each Operation Frequency
Wait Length
Setup wait length (set using bits SUWL2 to SUWL0)
VPSTB wait length (set using bits VSWL2 to VSWL0)
Caution These setting values are not guaranteed, so be sure to set the number of waits appropriate to the
system after verifying operation.
124
CHAPTER 5 BBR
Figure 5-6. NPB Strobe Wait Control Register (VSWC) (2/2)
Sets the VPSTB wait length.
VSWL2
VSWL1
VSWL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Remark
t
: Internal system clock (VBCLK) cycle
CLK
Setup wait
To 25 MHz
1
1
Preliminary User's Manual A14874EJ3V0UM
Function
VPSTB wait length
0 (no waits)
1×t
CLK
2×t
CLK
3×t
CLK
4×t
CLK
5×t
CLK
6×t
CLK
7×t
CLK
0.5 clock
1 clock
VPSTB wait
Operation Frequency
To 33 MHz
To 50 MHz
1
1
2
4
1.5 clock
To 81 MHz
To 100 MHz
2
2
5
6
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