Example Of Two-Cycle Single Transfer Timing (From Ram Connected To Vdb To Sdram Connected To Nt85E502) - Renesas NU85E Preliminary User's Manual

Figure 7-34. Example of Two-Cycle Single Transfer Timing (from RAM Connected to VDB to SDRAM Connected to NT85E502)
Notes 1. These are NT85E500 signals.
2-cycle single transfer
Read cycle Write cycle
VBCLK (Input)
SDCLK (Output) Note 1
VMTTYP1, VMTTYP0
0H 2H 3H
(Output)
VMA27 to VMA0 (Output)
VBDI31 to VBDI0 (Input) L
VBDO31 to VBDO0 (Output)
VMSTZ (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0
FH 0H
(Output)
VMCTYP2 to VMCTYP0
6H
(Output)
VMSEQ2 to VMSEQ0
0H
(Output)
VMSIZE1, VMSIZE0
2H
(Output)
VMLOCK (Output) L
VBDC (Output) L
VBDV (Output)
VDCSZ7 to VDCSZ0
FFH BFH
(Output)
VMWAIT (Input)
VMAHLD (Input) L
VMLAST (Input) L
DMARQn (Input) L
DMACTVn (Output)
DMTCOn (Output)
IRAMEN (Output)
A25 to A0 (Output) Note 2
DI31 to DI0 (Input) Note 2
DO31 to DO0 (Output) Note 1
SDRASZ (Output) Note 2
H
SDCASZ (Output) Note 2
SDWEZ (Output) Note 2
DQM3 to DQM0 (Output) Note 2
FH 0H
CSZ7 to CSZ0 (Output) Note 1
FFH BFH
CPU cycle 2-cycle single transfer
Read cycle Write cycle
0H 2H 3H 0H
FH 0H FH
6H
0H
2H
FFH BFH FFH
0H FH
FH
FFH BFH FFH
2. These are NT85E502 signals.