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7.5.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
These 8-bit registers are used to control the DMA transfer operation mode for DMA channels n (n = 0 to 3).
These registers can be read or written in 8-bit or 1-bit units (However, bit 7 can only be read and bits 2 and 1 can
only be written. If bits 2 and 1 are read, the value 0 is read).
Figure 7-7. DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3) (1/2)
7
6
DCHC0
TC0
0
DCHC1
TC1
0
DCHC2
TC2
0
DCHC3
TC3
0
Bit position
Bit name
7
TCn
3
MLEn
2
INITn
1
STGn
Cautions 1. Setting the MLEn bit (1) is valid only for a DMA transfer (hardware DMA) started by a
request generated by the DMARQn pin input. Therefore, the MLEn bit cannot be used
for DMA transfer (software DMA) started by setting the STGn bit (1) (the software DMA
operation with the MLEn bit set (1) is not guaranteed).
2. Bits 6 to 4 of the DCHC0 to DCHC3 registers must be set to 0. The operation when
these bits are set to 1 is not guaranteed.
Remark
n = 0 to 3
CHAPTER 7 DMAC
5
4
0
0
MLE0
0
0
MLE1
0
0
MLE2
0
0
MLE3
This is a status bit that indicates whether or not DMA transfer has ended for DMA channel n.
This bit can only be read. This bit is set (1) during the last transfer read cycle of DMA transfer.
It is cleared (0) when it is read.
0: DMA transfer has not ended
1: DMA transfer has ended
If this bit is set (1) when a terminal count is output, the ENn bit is not cleared (0), and the status
in which DMA transfer is enabled continues. Also, the next DMA transfer request is
acknowledged even if the TCn bit is not read. When DMA transfer is requested by setting the
STGn bit, the TCn bit must be read and cleared (0) even if the MLEn bit is set (1).
If this bit is cleared (0) when a terminal count is output, the ENn bit is cleared (0), and the status
in which DMA transfer is disabled occurs. When the next DMA transfer request is made, if the
TCn bit is read, the ENn bit must be set (1).
If this bit is set (1), the DMA transfer is forcibly terminated.
If this bit is set (1) during the status in which DMA transfer is enabled (TCn bit = 0, ENn bit = 1),
the DMA transfer begins.
Preliminary User's Manual A14874EJ3V0UM
3
2
1
INIT0
STG0
INIT1
STG1
INIT2
STG2
INIT3
STG3
Function
0
Address
After reset
EN0
FFFFF0E0H
00H
Address
After reset
EN1
FFFFF0E2H
00H
Address
After reset
EN2
FFFFF0E4H
00H
Address
After reset
EN3
FFFFF0E6H
00H
159
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