Renesas NU85E Preliminary User's Manual page 112

32-bit microprocessor core
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VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
(1,0)
VMLOCK (Output)
VMA27 to VMA0 (Output)
A.0
A.1
VMWRITE (Output)
VMBENZ3 to VMBENZ0 (Output)
VMCTYP2 to VMCTYP0 (Output)
VMSEQ2 to VMSEQ0 (Output)
(0,1,0)
(0,0,1)
VMSIZE1, VMSIZE0 (Output)
(1,0)
VMSTZ (Output)
VMBSTR (Output)
L
VBDC (Output)
VBDV (Output)
VDCSZ7 to VDCSZ0 (Output)
VDSELPZ (Output) H
VBDI31 to VBDI0 (Input)
D.0
VBDO31 to VBDO0 (Output)
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Word transfer
Figure 4-14. Read/Write Timing of Bus Slave Connected to VSB (12/12)
(l) 8-bit bus (little/big-endian, word/halfword/byte transfer)
Read
(1,1)
(1,0)
(1,1)
(1,0)
(1,1)
A.2
A.3
A.4
A.5
A.6
A.7
(1,1,1,0)
(0,0,1)
(0,0,0)
(0,0,1)
(0,0,0)
(0,0,1)
(0,1)
xxH
D.1
D.2
D.3
D.4
D.5
D.6
Halfword transfer
Idle
(1,0)
(0,0)
(1,0)
A.8
A.9
A.10
A.11
(1,1,1,1)
(0,0,0)
(0,1,0)
(0,0,1)
(0,0)
(1,0)
FFH
D.7
D.8
D.9
D.10
D.11
Byte transfer
Word transfer
Write
(1,1)
(1,0)
(1,1)
(1,0)
A.12
A.13
A.14
A.15
A.16
A.17
(1,1,1,0)
(0,0,1)
(0,0,0)
(0,0,1)
(0,0,0)
(0,1)
(0,0)
xxH
D.12
D.13
D.14
D.15
D.16
D.17
Halfword transfer
Byte transfer
Idle
(0,0)
(1,1,1,1)
FFH

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