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Figure No.
5-11
Read Modify Write Timing ...............................................................................................................................128
5-12
Retry Timing (Write).........................................................................................................................................128
5-13
Retry Timing (Read) ........................................................................................................................................129
5-14
Read/Write Timing of Bus Slave Connected to NPB .......................................................................................130
5-15
NPB Write Timing (Example of Timing of Data Write to CSC0 and CSC1 Registers) .....................................134
6-1
Power Save Function State Transition Diagram ..............................................................................................136
6-2
Power Save Control Register (PSC)................................................................................................................137
6-3
Command Register (PRCMD) .........................................................................................................................139
6-4
Connection of NU85E and Clock Control Circuit .............................................................................................144
6-5
Software STOP Mode Set/Cancel Timing Example.........................................................................................146
6-6
Hardware STOP Mode Set/Cancel Timing Example .......................................................................................148
7-1
DMA Source Address Registers 0H to 3H (DSA0H to DSA3H).......................................................................152
7-2
DMA Source Address Registers 0L to 3L (DSA0L to DSA3L) .........................................................................153
7-3
DMA Destination Address Registers 0H to 3H (DDA0H to DDA3H)................................................................154
7-4
DMA Destination Address Registers 0L to 3L (DDA0L to DDA3L) ..................................................................155
7-5
DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3) ..................................................................................156
7-6
DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3).......................................................................157
7-7
DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3)...........................................................................159
7-8
DMA Disable Status Register (DDIS) ..............................................................................................................160
7-9
DMA Restart Register (DRST).........................................................................................................................161
7-10
Buffer Register Configuration ..........................................................................................................................162
7-11
DMAC Bus Cycle State Transition Diagram ....................................................................................................165
7-12
Single Transfer Example 1 ..............................................................................................................................166
7-13
Single Transfer Example 2 ..............................................................................................................................166
7-14
Single Transfer Example 3 ..............................................................................................................................167
7-15
Single Transfer Example 4 ..............................................................................................................................167
7-16
Single-Step Transfer Example 1......................................................................................................................168
7-17
Single-Step Transfer Example 2......................................................................................................................168
7-18
Line Transfer Example 1..................................................................................................................................169
7-19
Line Transfer Example 2..................................................................................................................................169
7-20
Line Transfer Example 3..................................................................................................................................170
7-21
Line Transfer Example 4..................................................................................................................................170
7-22
Block Transfer Example...................................................................................................................................171
7-23
One-Time Transfer When Executing Single Transfers Using DMARQn Signal...............................................172
7-24
Example of Two-Cycle Transfer ......................................................................................................................173
7-25
Example of Flyby Transfer (Memory to I/O).....................................................................................................174
7-26
Timing Example of Terminal Count Signals (DMTCO3 to DMTCO0) ..............................................................176
7-27
Example of Terminal Count Signal Output (DMTCO3 to DMTCO0) ................................................................176
7-28
DMA Transfer Forcible Interruption Example...................................................................................................177
7-29
DMA Transfer Forcible Termination Example..................................................................................................178
7-30
Example of Two-Cycle Single Transfer Timing (Between External SRAMs Connected to NT85E500)...........181
7-31
Example of Two-Cycle Single-Step Transfer Timing (Between External SRAMs Connected to NT85E500) ..183
7-32
Example of Two-Cycle Line Transfer Timing (Between External SRAMs Connected to NT85E500)..............185
14
LIST OF FIGURES (2/3)
Title
Preliminary User's Manual A14874EJ3V0UM
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