Interrupt Mask Registers 0 To 3 (Imr0 To Imr3) - Renesas NU85E Preliminary User's Manual

(2) Interrupt mask registers 0 to 3 (IMR0 to IMR3)

The interrupt mask registers maintain the mask status of each maskable interrupt.
The PMKn bit of this register and the PMKn bit of the PICn register are linked (n = 0 to 63).
The IMRm register can be read or written in 16-bit units (m = 0 to 3).
When using the higher 8 bits of the IMRm register as the IMRmH register, and the lower 8 bits as the IMRmL
register, the IMRm register can be read or written in 8-bit or 1-bit units.
15 14 13
PMK PMK PMK PMK
IMR0
15 14 13
PMK PMK PMK PMK
IMR1
31 30 29
PMK PMK PMK PMK
IMR2
47 46 45
PMK PMK PMK PMK
IMR3
63 62 61
222
CHAPTER 8 INTC
Figure 8-9. Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
12 11 10 9 8 7
PMK PMK PMK PMK PMK
12 11 10 9 8 7
PMK PMK PMK PMK PMK
28 27 26 25 24 23
PMK PMK PMK PMK PMK
44 43 42 41 40 39
PMK PMK PMK PMK PMK
60 59 58 57 56 55
Preliminary User's Manual A14874EJ3V0UM
6 5 4 3 2
PMK PMK PMK PMK PMK PMK
6 5 4 3 2
PMK PMK PMK PMK PMK PMK
22 21 20 19 18
PMK PMK PMK PMK PMK PMK
38 37 36 35 34
PMK PMK PMK PMK PMK PMK
54 53 52 51 50
1 0
PMK Address After reset
1 0 FFFFF100H FFFFH
PMK Address After reset
17 16 FFFFF102H FFFFH
PMK Address After reset
33 32 FFFFF104H FFFFH
PMK Address After reset
49 48 FFFFF106H FFFFH