Renesas NU85E Preliminary User's Manual page 200

CHAPTER 7 DMAC
Figure 7-39 shows an example of the timing of a flyby line transfer (from external SRAM to external I/O
connected to the NT85E500). The settings of the registers in this figure are as follows.
[Register settings]
• DBCn register = 0007H (8 transfers)
• ASC register Note
= 0000H (No address setting wait states)
• BCC register
Note
= 0000H (No idle states)
• DWC0 register
Note
= 0000H (No wait states)
Note An NT85E500 register.
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