Renesas NU85E Preliminary User's Manual page 181

Figure 7-29. DMA Transfer Forcible Termination Example (2/2)
(b) The transfer is forcibly terminated during block transfer using DMA channel 1 and a transfer with
another condition is executed
DSA1, DDA1, DBC1,
DADC1, DCHC1
Set register
DMARQ1
(Input)
EN1 bit = 1
TC1 bit = 0
CPU CPU CPU
Remark Since the DSAn, DDAn, and DBCn registers are buffer registers with an FIFO configuration, the
values are retained even after a forcible termination. Also, the next transfer condition can be set
even during a DMA transfer. However, a setting in the DADCn register is ignored (See 7.6 Next
Address Setting Function).
CHAPTER 7 DMAC
DSA1, DDA1, DCHC1
DBC1 (INIT1 bit = 1)
Set register
CPU DMA1 DMA1 DMA1 DMA1 DMA1
Preliminary User's Manual A14874EJ3V0UM
DADC1,
DCHC1
Set register Set register
→ →
EN1 bit 0 EN1 bit 1
TC1 bit = 0 TC1 bit = 0
DMA1 CPU CPU CPU CPU DMA1
DMA channel 1 transfer is forcibly
terminated and the bus is released
→
EN1 bit 0
→
TC1 bit 1
DMA1 DMA1 CPU
DMA channel 1
terminal count
179