Csc0 And Csc1 Register Setting Example (256 Mb Mode) - Renesas NU85E Preliminary User's Manual

32-bit microprocessor core
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Examples 2. The following figure shows an example of CSC0 and CSC1 register settings for 256 MB mode and
the memory map after the settings are made.
Figure 4-4. CSC0 and CSC1 Register Setting Example (256 MB Mode) (1/2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSC0
x
x
x
Notes 1. Since the high priority signals from the bit 0, 1, 10, and 11 settings (VDCSZ0 and VDCSZ2)
correspond to banks 0 to 3, the setting in banks 0 to 3, which are included in area 0, become invalid.
Notes
2. Since the high priority signal from the bit 0 setting (VDCSZ0) corresponds to bank 0, the setting
becomes invalid.
Notes
3. Since the high priority signal from the bit 1 setting (VDCSZ0) corresponds to bank 1, the setting
becomes invalid.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSC1
x
x
x
x 0 1 1 1 x x x x 0
Notes 1. Since the high priority signals from the bit 1, 2, and 8 settings (VDCSZ5 and VDCSZ7) correspond
to banks 13 to 15, the settings in banks 13 to 15, which are included in area 3, become invalid
(Since bank 12 has no corresponding VDCSZn signal, its setting does not become invalid).
2. Since the high priority signal from the bit 1 setting (VDCSZ7) corresponds to bank 14, the setting
becomes invalid.
3. Since the high priority signal from the bit 2 setting (VDCSZ7) corresponds to bank 13, the setting
becomes invalid.
82
CHAPTER 4 BCU
(a) CSC0 register settings
x 1 1 1 1 x x x x 0
(b) CSC1 register settings
Preliminary User's Manual A14874EJ3V0UM
0
1
1
VDCSZn signals that become active
VDCSZ0 (when accessing bank 0)
VDCSZ0 (when accessing bank 1)
VDCSZ1 (when accessing area 0)
VDCSZ2 (when accessing bank 0)
VDCSZ2 (when accessing bank 1)
VDCSZ2 (when accessing bank 2)
VDCSZ2 (when accessing bank 3)
VDCSZ3 (when accessing area 1)
1
1
0
VDCSZn signals that become active
VDCSZ7 (when accessing bank 14)
VDCSZ7 (when accessing bank 13)
VDCSZ6 (when accessing area 3)
VDCSZ5 (when accessing bank 15)
VDCSZ5 (when accessing bank 14)
VDCSZ5 (when accessing bank 13)
VDCSZ4 (when accessing area 2)
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3

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