Chapter 1 Introduction; Outline - Renesas NU85E Preliminary User's Manual

The NU85E Family consists of CPU cores that feature on-chip the "V850E1" 32-/16-bit RISC type CPU and
peripheral I/Os, and are designed for embedding in ASICs. The V850E1 can execute almost all instructions in 1
clock through 5-stage pipeline control based on the RISC architecture.
provides on-chip 2 types of external bus interfaces for connection to high- and low-speed peripheral I/Os, as well as
functions to interface with ROM, RAM, an instruction cache, and a data cache. This product, the "NU85E", is a CPU
core that has, among other on-chip features, a DMA controller and an interrupt controller.

1.1 Outline

(1) "V850E1" CPU
The NU85E is equipped with the "V850E1", which is a RISC type CPU that utilizes a five-stage pipeline
technique. Two-byte basic instructions and instructions for high-level language support increase the efficiency of
object code generated by the C compiler and reduce the program size.
In addition, to increase the speed of multiplication processing, the NU85E contains an on-chip high-speed
hardware multiplier capable of executing 32-bit × 32-bit operations.
(2) Bus interfaces
The NU85E provides the following two types of bus interface for connection with peripheral macros or user logic.
• V850E system bus (VSB)
• NEC peripheral I/O bus (NPB)
The VSB, which is synchronized with the system clock, is the bus to be used for connection with high-speed
peripheral macros such as a memory controller (MEMC) or macros operating as bus master (DMAC, DSP, etc.).
The NPB, which operates asynchronously with the system clock, is to be used for connection with relatively low-
speed peripheral macros such as a timer or asynchronous serial interface (UART).
A V850E fetch bus (VFB), which can be directly coupled with ROM, and a V850E data bus (VDB), which can be
directly coupled with RAM, are also provided.
In addition, since the NU85E contains on-chip special purpose interfaces for the instruction cache, data cache,
and run control unit (RCU), each macro can be directly coupled.
(3) On-chip peripheral I/O
The NU85E contains an on-chip DMA control unit (DMAC) for controlling DMA transfers, an on-chip interrupt
control unit (INTC) for controlling interrupt requests, and an on-chip standby control unit (STBC) for controlling
the power save function.

CHAPTER 1 INTRODUCTION

Preliminary User's Manual A14874EJ3V0UM
Furthermore, the NU85E Family also
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