Renesas NU85E Preliminary User's Manual page 82

Figure 4-3. CSC0 and CSC1 Register Setting Example (64 MB Mode) (2/3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSC1 1 1 1 1 0 1 1 1 1 1 1 0 0
Notes 1. Since the high priority signal from the bit 2 setting (VDCSZ7) corresponds to bank 13, only the
setting in bank 12 becomes valid.
2. Since the high priority signal from the bit 1 setting (VDCSZ7) corresponds to bank 14, the setting in
bank 14 becomes invalid.
3. Since the high priority signal from the bit 2 setting (VDCSZ7) corresponds to bank 13, the setting in
bank 13 becomes invalid.
4. Since the high priority signal from the bit 5 setting (VDCSZ6) corresponds to bank 12, the setting in
bank 12 becomes invalid.
5. Since the high priority signal from the bit 8 setting (VDCSZ5) corresponds to bank 15, the setting in
bank 15 becomes invalid.
6. Since the high priority signal from the bit 7 setting (VDCSZ6) corresponds to bank 10, the setting in
bank 10 becomes invalid.
7. Since the high priority signal from the bit 6 setting (VDCSZ6) corresponds to bank 11, the setting in
bank 11 becomes invalid.
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CHAPTER 4 BCU
(b) CSC1 register settings
1 1 0
VDCSZ7 (when accessing bank 14)
VDCSZ7 (when accessing bank 13)
VDCSZ6 (when accessing bank 12 or 13)
VDCSZ6 (when accessing bank 11)
VDCSZ6 (when accessing bank 10)
VDCSZ5 (when accessing bank 15)
VDCSZ5 (when accessing bank 14)
VDCSZ5 (when accessing bank 13)
VDCSZ4
(when accessing bank 12, 13, 14, or 15)
VDCSZ4 (when accessing bank 10 or 11)
VDCSZ4 (when accessing bank 9)
VDCSZ4 (when accessing bank 8)
Preliminary User's Manual A14874EJ3V0UM
VDCSZn signals that become active
Note 2
Note 3
Note 1
Notes 2, 3, 4, 5
Notes 6, 7