Restore; Reti Instruction Processing Format - Renesas NU85E Preliminary User's Manual

8.2.2 Restore

(1) NMI0
Control is returned from NMI0 servicing according to the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing and shifts control to the
restored PC address.
<1> Since the EP bit of the PSW is 0 and the NP bit is 1, fetch the restored PC and PSW from the FEPC and
FEPSW.
<2> Shift control to the fetched restored PC address and PSW status.
Figure 8-3 shows the processing format of the RETI instruction.
Caution If the PSW.EP bit or PSW.NP bit is changed by the LDSR instruction during NMI0 servicing,
then in order to restore the PC and PSW correctly when control is returned according to the
RETI instruction, the LDSR instruction must be used to return PSW.EP to 0 and PSW.NP to 1
immediately before executing the RETI instruction.
Remark The solid line indicates the CPU processing flow.
(2) NMI1, NMI2
Restoring by RETI instruction is not possible. Perform a system reset according to DCRESZ input after interrupt
servicing.
CHAPTER 8 INTC
Figure 8-3. RETI Instruction Processing Format
RETI instruction
1
PSW.EP
0
PSW.NP
0
← EIPC
PC
PSW ← EIPSW
Original processing restored
Preliminary User's Manual A14874EJ3V0UM
1
← FEPC
PC
PSW ← FEPSW
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