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2.2.4 DMAC pins
(1) IDMASTP (input)
This is the DMA transfer forcible interrupt input pin.
synchronization with the rising edge of the VBCLK signal.
To restart transfer, set (1) the EN bit of the DRST register after inputting a low level to this pin.
(2) DMARQ3 to DMARQ0 (input)
These are the DMA transfer request input pins.
Input an active level (high level) in synchronization with the rising edge of the VBCLK signal, and continue
inputting until the corresponding DMACTVn signal becomes high level (n = 3 to 0).
(3) DMTCO3 to DMTCO0 (output)
These are the terminal count (DMA transfer completion) output pins. A one-clock high level is output from these
pins when the final DMA transfer is performed.
The high level is output in synchronization with the rising edge of the VBCLK signal.
(4) DMACTV3 to DMACTV0 (output)
These are the DMA acknowledge output pins. These pins become active (high-level output) during a 2-cycle
transfer VSB read or VSB write cycle, or during a flyby transfer.
2.2.5 INTC pins
(1) DCNMI2 to DCNMI0 (input)
These are the non-maskable interrupt request (NMI) input pins. When a rising edge is input, a non-maskable
interrupt is generated.
(2) INT63 to INT0 (input)
These are the maskable interrupt request input pins. When a rising edge is input, a maskable interrupt is
generated.
2.2.6 VFB pins
(1) IROMA19 to IROMA2 (output)
These pins constitute a bus from which addresses are output to ROM.
(2) IROMZ31 to IROMZ0 (input)
These pins constitute a bus to which data is input from ROM.
(3) IROMEN (output)
This is the pin from which access enable signals are output to ROM. It changes in synchronization with the
falling edge of the VBCLK signal.
(4) IROMWT (input)
This is the pin to which wait signals are input from ROM. A high level is input during the wait period.
(5) IROMCS, IROMIA, IROMAE (output)
These are NEC reserved pins. Leave them open.
36
CHAPTER 2 PIN FUNCTIONS
Input an active level (high level) of two clocks in
Preliminary User's Manual A14874EJ3V0UM
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