System Registers - Renesas NU85E Preliminary User's Manual

3.2.2 System registers

System registers control the status of the CPU and hold interrupt information.
To read from or write to these system registers, specify the system register number (see Table 3-2) indicated by
the system register load or store instruction (LDSR or STSR instruction).
Register Name
No.
0 EIPC Register for
saving status
when interrupt
1 EIPSW
occurs
2 FEPC Register for
saving status
when NMI
3 FEPSW
occurs
4 ECR Interrupt source
register
5 PSW Program status
word
16 CTPC Register for
saving status
when CALLT is
17 CTPSW
executed
18 DBPC Register for
saving status
when exception
is trapped
19 DBPSW
20 CTBP CALLT base
pointer
6 to 15, Reserved numbers for future function expansion (if these are accessed, operation is not
21 to 31 guaranteed).
Remark Yes: Access enabled No: Access disabled
Note Since there is only one set of these registers, their contents must be saved by the program when multiple
interrupts are permitted.
CHAPTER 3 CPU
Table 3-2. List of System Registers
This register saves the value of the PC when a software
exception or interrupt occurs.
This register saves the value of the PSW when a
Note
software exception or interrupt occurs.
This register saves the value of the PC when a non-
maskable interrupt (NMI) occurs.
This register saves the value of the PSW when a non-
maskable interrupt (NMI) occurs.
This register holds information about the source when an
exception or interrupt occurs. The exception code of a
non-maskable interrupt (NMI) is set in the higher 16 bits of
this register (FECC). The exception code of an exception
or maskable interrupt is set in the lower 16 bits (EICC)
(See Figure 3-3).
This is a collection of flags indicating the program status
(instruction execution result) or CPU status (See Figure
3-4).
This register saves the value of the PC when a CALLT
instruction is executed.
This register saves the value of the PSW when a CALLT
instruction is executed.
This register saves the value of the PC when an
exception trap is generated due to the detection of an
illegal instruction code.
This register saves the value of the PSW when an
exception trap is generated due to the detection of an
illegal instruction code.
This is used to specify the table address or generate the
target address.
Preliminary User's Manual A14874EJ3V0UM
Operation Whether or Not Operand
Can be Specified
LDSR STSR
Instruction Instruction
Yes Yes
Yes Yes
Yes Yes
Yes Yes
No Yes
Yes Yes
Yes Yes
Yes Yes
No Yes
No Yes
Yes Yes
No No
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