Vdb Pins - Renesas NU85E Preliminary User's Manual

2.2.7 VDB pins

(1) IRAMA27 to IRAMA2 (output)
These pins constitute a bus from which addresses are output to RAM. The IRAMA27 to IRAMA16 signals are
output for the data cache. Therefore, they do not have to be decoded when RAM is connected.
(2) IRAMZ31 to IRAMZ0 (input)
These pins constitute a bus to which data is input from RAM.
(3) IRAOZ31 to IRAOZ0 (output)
These pins constitute a bus from which data is output to RAM.
(4) IRAMEN (output)
This is the pin from which access enable signals are output to RAM. It changes in synchronization with the
falling edge of the VBCLK signal.
(5) IRAMWR3 to IRAMWR0 (output)
These are the pins from which write enable signals are output to RAM. They are high-level active pins that
indicate the enabled byte data among the output data bus pins (IRAOZ31 to IRAOZ0).
Active (High-Level Output) Signal
IRAMWR0
IRAMWR1
IRAMWR2
IRAMWR3
(6) IRAMRWB (output)
This is the pin from which the read/write status is output to RAM. During reading, a high-level signal is output.
During writing, a low-level signal is output.
(7) IRAMWT (input)
This is the pin to which wait signals are input from the data cache. A high level is input during the wait period.
CHAPTER 2 PIN FUNCTIONS
Table 2-6. IRAMWR3 to IRAMWR0 Signals
IRAOZ7 to IRAOZ0
IRAOZ15 to IRAOZ8
IRAOZ23 to IRAOZ16
IRAOZ31 to IRAOZ24
Preliminary User's Manual A14874EJ3V0UM
Enabled Byte Data
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