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(9) IFIUNCH0 (input)
This is the instruction cache setting input pin.
The instruction cache is enabled or disabled as follows according to the input level to this pin.
• Low level: Instruction cache is enabled
• High level: Instruction cache is disabled
(10) PHEVA (input)
This is the peripheral evaluation chip mode setting input pin. A high level is input when the ASIC in which the
NU85E has been incorporated is used as a peripheral evaluation chip.
(11) IFIROBE, IFIROPR, IFIRASE, IFIRABE, IFIMODE3, IFIMODE2, IFIUSWE, FCOMB (input)
These are NEC reserved pins. Always input low-level signals.
2.2.13 Test mode pins
(1) TBI39 to TBI0 (input)
These pins constitute an input test bus.
(2) TBO34 to TBO0 (output)
These pins constitute an output test bus.
(3) TEST (input)
This is the test bus control input pin.
(4) BUNRI (input)
This is the input pin for selecting normal or test mode.
(5) BUNRIOUT (output)
This is the status output pin that indicates the test mode status.
The level of the BUNRI pin (input) is output as is.
(6) PHTDO1, PHTDO0 (input)
These pins are the peripheral macro test input pins.
(7) TESEN (output)
This is the enable output pin for setting peripheral macros to test mode.
(8) VPTCLK (output)
This is the clock output pin for peripheral macro tests.
(9) PHTDIN1, PHTDIN0 (output)
These are the peripheral macro test output pins.
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CHAPTER 2 PIN FUNCTIONS
Preliminary User's Manual A14874EJ3V0UM
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