Renesas NU85E Preliminary User's Manual page 119

(Writing the 32-bit data "12345678H" to address "200003H")
VBCLK (Input)
VMTTYP1, VMTTYP0
(1,0)
(Output)
VMLOCK (Output)
VMA27 to VMA0 (Output)
VMWRITE (Output) H
VMBENZ3 to VMBENZ0
(Output)
VMCTYP2 to VMCTYP0
(Output)
VMSEQ2 to VMSEQ0
(Output)
VMSIZE1, VMSIZE0
(Output)
VMSTZ (Output)
VDCSZ7 to VDCSZ0
(Output)
VBDI31 to VBDI0
L
(Input)
VBDO31 to VBDO0
(Output)
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
Remarks 1. O mark: Sampling timing
: Arbitrary input level
2. The timing seen from the NU85E when the NU85E has the bus access right is shown.
CHAPTER 4 BCU
Figure 4-18. Misalign Access Timing (2/2)
(b) Timing for access to odd addresses
Byte write Halfword write
(1,1) (1,0)
200003H
(0,1,1,1)
(0,0)
78xxxxxxH
Preliminary User's Manual A14874EJ3V0UM
Byte write
(1,1) (1,0)
200004H
(1,1,0,0)
(0,1,0)
(0,0,0)
(0,1)
xxxx3456H
(1,1)
200006H
(1,0,1,1)
(0,0)
xx12xxxxH
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