Programmable Peripheral I/O Area; Peripheral I/O Area And Programmable Peripheral I/O Area - Renesas NU85E Preliminary User's Manual

5.1 Programmable Peripheral I/O Area

The NU85E has a 4 KB peripheral I/O area that is allocated in advance in the address space and a 12 KB
programmable peripheral I/O area that can be allocated at arbitrary addresses according to register settings (See 4.4
Programmable Peripheral I/O Area Selection Function).
If the peripheral I/O area or programmable peripheral I/O area in the memory map shown in Figure 5-3 is
accessed, the NPB becomes active.
The programmable peripheral I/O area is set by the peripheral I/O area select control register (BPC).
Figure 5-3. Peripheral I/O Area and Programmable Peripheral I/O Area
(a) 64 MB mode
3FFFFFFH
Peripheral I/O area
3FFF000H
3FFEFFFH
xxxnFFFH
(n = yy11B)
xxxm000H
(m = yy00B)
0000000H
Note See Figure 3-8 Data Area (256 MB Mode).
Remarks 1. xxx: Setting according to the PA13 to PA02 bits of the BPC register
yy: Setting according to the PA01 and PA00 bits of the BPC register
2. Since the areas indicated by "same area" are linked, if data is written in one area, data having
the same contents is also written in the other area.
120
CHAPTER 5 BBR
Same
(4 KB)
area
(4 KB)
Programmable
peripheral I/O area
(12 KB)
Preliminary User's Manual A14874EJ3V0UM
(b) 256 MB mode
FFFFFFFH
Peripheral I/O area
FFFF000H
FFFEFFFH
Same
(RAM area)
area
Note
xxxnFFFH
(n = yy11B)
Programmable
peripheral I/O area
(12 KB)
xxxm000H
(m = yy00B)
3FFF000H
3FFEFFFH
0000000H
Same
(4 KB)
area
(4 KB)