Renesas NU85E Preliminary User's Manual page 98

32-bit microprocessor core
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(3) Byte enable
The bus master uses the VMBENZ3 to VMBENZ0 signals to indicate the byte data among the data obtained by
quartering the data bus (VBDI31 to VBDI0 and VBDO31 to VBDO0) into byte units.
Active (Low-Level Output) Signal
VMBENZ0
VMBENZ1
VMBENZ2
VMBENZ3
(4) Transfer size
The bus master uses the VMSIZE1 and VMSIZE0 signals to indicate the transfer size.
(5) Sequential status
The bus master uses the VMSEQ2 to VMSEQ0 signals to indicate the "burst transfer length" when a burst
transfer starts, to indicate "continuous" during a burst transfer, and to indicate "single transfer" at the end of the
burst transfer.
VMSEQ2
VMSEQ1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note This is output during continuous 2 times, or continuous 4, 8, 16, 32, 64, or 128 times transfer.
Remark 0: low-level 1: high-level
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CHAPTER 4 BCU
Table 4-3. VMBENZ3 to VMBENZ0 Signals
Table 4-4. VMSIZE1 and VMSIZE0 Signals
VMSIZE1
VMSIZE0
0
0
Byte (8 bits)
0
1
Halfword (16 bits)
1
0
Word (32 bits)
1
1
(Reserved for future function expansion)
Remark 0: low-level 1: high-level
Table 4-5. VMSEQ2 to VMSEQ0 Signals
VMSEQ0
0
Single transfer
1
Continuous (indicates that the next transfer address is related to the current
transfer address)
0
Continuous 4 times (burst transfer length: 4)
1
Continuous 8 times (burst transfer length: 8)
0
Continuous 16 times (burst transfer length: 16)
1
Continuous 32 times (burst transfer length: 32)
0
Continuous 64 times (burst transfer length: 64)
1
Continuous 128 times (burst transfer length: 128)
Preliminary User's Manual A14874EJ3V0UM
Enabled Byte Data
VBDI7 to VBDI0, VBDO7 to VBDO0
VBDI15 to VBDI8, VBDO15 to VBDO8
VBDI23 to VBDI16, VBDO23 to VBDO16
VBDI31 to VBDI24, VBDO31 to VBDO24
Explanation
Sequential Status
Note

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