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A-D Comparator characteristics
(V
= 5 V ± 10 %, V
CC
Symbol
—
Resolution
—
Absolute accuracy
Note: When V
= 5 V, 1 LSB = 5/64 V.
CC
2
Multi-master I
C-BUS bus line characteristics
Symbol
t
Bus free time
BUF
t
Hold time for START condition
HD:STA
t
LOW period of SCL clock
LOW
t
Rising time of both SCL and SDA signals
R
Data hold time
t
HD:DAT
t
HIGH period of SCL clock
HIGH
t
Falling time of both SCL and SDA signals
F
t
Data set-up time
SU:DAT
Set-up time for repeated START condition
t
SU:STA
Set-up time for STOP condition
t
SU:STO
Note: C
= total capacitance of 1 bus line
b
SDA
t
BUF
P
S
SCL
t
HD
Fig. 3.1.1 Definition diagram of timing on multi-master I
ELECTRICAL CHARACTERISTICS
= 0 V, f(X
) = 8 MHz, T
SS
IN
Parameter
Parameter
t
LOW
t
R
:
t
:
t
STA
HD
DAT
HIGH
7220 Group User's Manual
= –10 °C to 70 °C, unless otherwise noted)
a
Test conditions
Standard clod mode High-speed clock mode
Min.
4.7
4.0
4.7
4.0
250
4.7
4.0
t
t
F
Sr
t
:
t
:
SU
DAT
SU
STA
2
C-BUS
3.1 Electrical characteristics
Limits
Min.
Typ.
0
±1
Max.
Typ.
1.3
0.6
1.3
1000
20+0.1C
0
0
0.6
300
20+0.1C
100
0.6
0.6
t
:
:
SU
STO
HD
STA
S
: Start condition
Sr
: Restart condition
P
: Stop condition
Unit
Max.
6
bits
±2
LSB
Unit
Max.
µ s
µ s
µ s
ns
300
b
µ s
0.9
µ s
ns
300
b
ns
µ s
µ s
P
3-5
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