ST STM32WL55JC Reference Manual page 1304

Serial peripheral interface / integrated interchip sound (SPI/I2S)
37.9 SPI and I2S registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR
in addition can be accessed by 8-bit access.
37.9.1 SPI control register 1 (SPIx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
BIDI CRC CRCN
BIDIOE
MODE EN EXT
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Bit 15 BIDIMODE: Bidirectional data mode enable.
Note: This bit is not used in I
Bit 14 BIDIOE: Output enable in bidirectional mode
Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
Bit 13 CRCEN: Hardware CRC calculation enable
Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation.
Bit 12 CRCNEXT: Transmit CRC next
Note: This bit has to be written as soon as the last data is written in the SPIx_DR register.
Bit 11 CRCL: CRC length
Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation.
1304/1454
12 11 10 9
RX
CRCL SSM
ONLY
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This bit enables half-duplex communication using common single bidirectional data line.
Keep RXONLY bit clear when bidirectional mode is active.
0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional
mode.
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
This bit is not used in I
0: CRC calculation disabled
1: CRC calculation enabled
This bit is not used in I
0: Next transmit value is from Tx buffer.
1: Next transmit value is from Tx CRC register.
This bit is not used in I
This bit is set and cleared by software to select the CRC length.
0: 8-bit CRC length
1: 16-bit CRC length
This bit is not used in I
8 7 6
LSB
SSI SPE
FIRST
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2
S mode.
2
S mode.
2
S mode.
2
S mode.
2
S mode.
RM0453 Rev 2
5 4 3 2
BR[2:0] MSTR
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RM0453
1 0
CPOL CPHA
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