ST STM32WL55JC Reference Manual page 1341

RM0453
38.5.6 AP identification register (AP_IDR)
Address offset: 0xFC
Reset value: 0x2477 0011 (AP0)
Reset value: 0x6477 0001 (AP1)
31 30 29
REVISION[3:0]
r r r
15 14 13
Res. Res. Res. Res.
Bits 31:28 REVISION[3:0]: revision
0x2: CPU1 Cortex-M4 r0p3
0x6: CPU2 Cortex-M0+ r0p7
Bits 27:24 JEDECBANK[3:0]: JEDEC bank
0x4: Arm
Bits 23:17 JEDECCODE[6:0]: JEDEC code
0x3B: Arm
Bit 16 MEMAP: memory access port
0x1: Standard register map
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IDENTITY[7:0]: AP type
0x11: CPU1 (Cortex-M4) AHB-AP (AP0)
0x01: CPU2 (Cortex-M0+) AHB-AP (AP1)
Others: reserved
38.5.7 AP register map and reset values
These registers are not on the CPU memory bus and are only accessed through SW-DP
and JTAG-DP debug interface.
The access port address is 8-bit wide, defined by debug port register
DP_SELECTR.APBANKSEL[3:0] field and by JTAG-DP register DPACC or SW-DP packet
request A[3:2] field.
Offset Register name
AP_CSWR
0x00
Reset value
AP_TAR
0x04
Reset value
28 27 26 25
JEDECBANK[3:0]
r r r r
12 11 10 9
Res. Res. Res.
Table 270. AP register map and reset values
PROT[4:0]
0 0 0 0 1 1
0 0 0 0 0 0 0 0
24 23 22
r r r
8 7 6
Res.
r r
0
TA[31:0]
0 0 0 0 0 0 0 0 0
RM0453 Rev 2
Debug support (DBG)
21 20 19 18
JEDECCODE[6:0]
r r r r
5 4 3 2
IDENTITY[7:0]
r r r r
MODE[3:0]
0 0 0 0 0 1
0 0 0 0 0 0 0 0 0
17 16
MEMAP
r r
1 0
r r
0 0 0 0 0
0 0 0 0 0 0
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