ST STM32WL55JC Reference Manual page 1305

RM0453
Bit 10 RXONLY: Receive only mode enabled.
Note: This bit is not used in I
Bit 9 SSM: Software slave management
Note: This bit is not used in I
Bit 8 SSI: Internal slave select
Note: This bit is not used in I
Bit 7 LSBFIRST: Frame format
Note: 1. This bit should not be changed when communication is ongoing.
Bit 6 SPE: SPI enable
Note: When disabling the SPI, follow the procedure described in
Bits 5:3 BR[2:0]: Baud rate control
Note: These bits should not be changed when communication is ongoing.
Bit 2 MSTR: Master selection
Note: This bit should not be changed when communication is ongoing.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
This bit enables simplex communication using a single unidirectional line to receive data
exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also
useful in a multislave system in which this particular slave is not accessed, the output from
the accessed slave is not corrupted.
0: Full-duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the I/O value of the NSS pin is ignored.
0: data is transmitted / received with the MSB first
1: data is transmitted / received with the LSB first
2. This bit is not used in I
0: Peripheral disabled
1: Peripheral enabled
SPI on page 1270.
This bit is not used in I
000: f /2
PCLK
001: f /4
PCLK
010: f /8
PCLK
011: f /16
PCLK
100: f /32
PCLK
101: f /64
PCLK
110: f /128
PCLK
111: f /256
PCLK
These bits are not used in I
0: Slave configuration
1: Master configuration
This bit is not used in I
2
S mode.
2
S mode and SPI TI mode.
2
S mode and SPI TI mode.
2
S mode and SPI TI mode.
2
S mode.
2
S mode.
2
S mode.
RM0453 Rev 2
Procedure for disabling the
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