Figure 363. I2S Block Diagram - ST STM32WL55JC Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
•
In reception mode:
If data 0x8EAA33 is received:
Figure 367. I
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the
operation shown in
Figure 368. Example of 16-bit data frame extended to 32-bit channel frame
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Figure 365. Transmitting 0x8EAA33
First write to Data register
0x8EAA
Figure 366. Receiving 0x8EAA33
First read to Data register
0x8EAA
2
S Philips standard (16-bit extended to 32-bit packet frame)
CK
WS
Transmission
16-bit data
SD
MSB
Channel left 32-bit
Figure 368 is required.
Second write to Data register
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything
Second read to Data register
0x33XX
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything
Reception
16-bit remaining 0 forced
LSB
Only one access to SPIx_DR
0x76A3
RM0453 Rev 2
0x33XX
Channel right
RM0453
MS19593V2
MS19594V1
MS19599V1
MS19595V1