ST STM32WL55JC Reference Manual page 1343

RM0453
A DWT comparator compares the value held in its DWT_COMPxR registers with one of the
following:
•
a data address
•
an instruction address
•
a data value
•
the cycle count value, for comparator 0 only.
For address matching, the comparator can use a mask, so it matches a range of addresses.
On a successful match, the comparator generates one of the following:
•
one or more DWT data trace packets, containing one or more of:
–
–
–
•
a watchpoint debug event, on either the PC value or the accessed data address
•
a CMPMATCH[N] event that signals the match outside the DWT unit
A watchpoint debug event either generates a DebugMonitor exception or causes the
processor to halt execution and enter Debug state.
For more details on how to use the DWT, refer to the Arm
Manual [5].
38.6.1 DWT control register (DWT_CTRLR)
Address offset: 0x000
Reset value: 0x4000 0000
31 30 29 28
NUMCOMP[3:0]
r r r r
15 14 13 12
PCSAMPL
Res. Res. Res.
ENA
rw
Bits 31:28 NUMCOMP[3:0]: number of comparators implemented (read only)
0x4: Four comparators
Bit 27 NOTRCPKT: trace sampling and exception tracing support (read only)
0: Supported
Bit 26 NOEXTTRIG: external match signal, CMPMATCH support (read only)
0: Supported
Bit 25 NOCYCCNT: cycle counter support (read only)
0: Supported
Bit 24 NOPRFCNT: profiling counter support (read only)
0: Supported
Bit 23 Reserved, must be kept at reset value.
the address of the instruction that caused a data access
an address offset, bits[15:0] of the data access address
the matched data value
27 26 25
NOTR NOEXT NOCYC NOPRF
CPKT TRIG CNT
r r r
11 10 9
SYNCTAP[1:0] CYCTAP
rw rw rw
24 23 22 21
CYCEV FOLDE
Res.
CNT TENA VTENA
r rw rw
8 7 6 5
POSTINIT[3:0]
rw rw rw rw
RM0453 Rev 2
Debug support (DBG)
®
v7-M Architecture Reference
20 19 18
LSUEV SLEEPEVT EXCEVT
TENA ENA ENA
rw rw rw
4 3 2
POSTPRESET[3:0]
rw rw rw
17 16
CPIEV EXCTRC
TENA ENA
rw rw
1 0
CYCCNT
ENA
rw rw
1343/1454
1441