ST STM32WL55JC Reference Manual page 1310

Serial peripheral interface / integrated interchip sound (SPI/I2S)
37.9.4 SPI data register (SPIx_DR)
Address offset: 0x0C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DR[15:0]: Data register
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
37.9.5 SPI CRC polynomial register (SPIx_CRCPR)
Address offset: 0x10
Reset value: 0x0007
15 14 13
rw rw rw
Bits 15:0 CRCPOLY[15:0]: CRC polynomial register
Note: The polynomial value should be odd only. No even value is supported.
37.9.6 SPI Rx CRC register (SPIx_RXCRCR)
Address offset: 0x14
Reset value: 0x0000
15 14 13
r r r
1310/1454
12 11 10 9
rw rw rw rw
Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 37.5.9: Data transmission and reception
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.
12 11 10 9
rw rw rw rw
This register contains the polynomial for the CRC calculation.
The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be
configured as required.
12 11 10 9
r r r r
8 7 6
DR[15:0]
rw rw rw
procedures).
8 7 6
CRCPOLY[15:0]
rw rw rw
8 7 6
RXCRC[15:0]
r r r
RM0453 Rev 2
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
5 4 3 2
r r r r
RM0453
1 0
rw rw
1 0
rw rw
1 0
r r