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Debug support (DBG)
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 EXCCNT[7:0]: exception overhead cycle counter
Counts the number of cycles spent in exception processing.
38.6.5
DWT sleep count register (DWT_SLPCNTR)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 SLEEPCNT[7:0]: sleep cycle counter
Counts the number of cycles spent in sleep mode (WFI, WFE, sleep-on-exit).
38.6.6
DWT LSU count register (DWT_LSUCNTR)
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 LSUCNT[7:0]: load store counter
Counts additional cycles required to execute load and store instructions.
1346/1454
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 2
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
SLEEPCNT[7:0]
rw
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
LSUCNT[7:0]
rw
rw
rw
rw
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
rw
rw
rw
rw
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