ST STM32WL55JC Reference Manual page 1303

RM0453
synchronization is lost, the following steps are required to recover from this state and
resynchronize the external master device with the I2S slave device:
1. Disable the I2S.
2. Enable it again when the correct level is detected on the WS line (WS line is high in I
mode or low for MSB- or LSB-justified or PCM modes.
Desynchronization between master and slave devices may be due to noisy environment on
the CK communication clock or on the WS frame synchronization line. An error interrupt can
be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.
37.7.9 DMA features
2
In I S mode, the DMA works in exactly the same way as it does in SPI mode. There is no
difference except that the CRC feature is not available in I
transfer protection system.
37.8 I2S interrupts
Table 258
Transmit buffer empty flag
Receive buffer not empty flag
Overrun error
Underrun error
Frame error flag
Serial peripheral interface / integrated interchip sound (SPI/I2S)
provides the list of I2S interrupts.
Table 258. I2S interrupt requests
Interrupt event Event flag
TXE
RXNE
OVR
UDR
FRE
RM0453 Rev 2
2
S mode since there is no data
Enable control bit
TXEIE
RXNEIE
ERRIE
2
S
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