Figure 372. Msb Justified 16-Bit Extended To 32-Bit Packet Frame; Figure 373. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy; Figure 374. Lsb Justified 24-Bit Frame Length - ST STM32WL55JC Reference Manual

RM0453
Figure 379. PCM standard waveforms (16-bit extended to 32-bit packet frame)
Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.
37.7.3 Start-up description
TheFigure 380
SPI/I2S is enabled (via I2SE bit). It shows as well the effect of CKPOL on the generated
signals.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
CK
WS
short frame
Up to 13-bits
WS
long frame
16 bits
SD
MSB
shows how the serial interface is handled in MASTER mode, when the
RM0453 Rev 2
LSB
MS30107V1
1293/1454
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