Table 269. Mem-Ap Registers - ST STM32WL55JC Reference Manual

Debug support (DBG)
38.5.1 AP control/status word register (AP_CSWR)
Address offset: 0x00
Reset value: 0x2300 0040
31 30 29
Res. SPROT Res.
r
15 14 13
Res. Res. Res. Res.
Bit 31 Reserved, must be kept at reset value.
Bit 30 SPROT: secure transfer request
In the AHB-APs, this field sets the protection attribute HPROT[6] of the bus transfer.
0: If SPIDEN is high, secure transfer. If SPIDEN is low, non-secure transfer
1: Non-secure transfer
Bit 29 Reserved, must be kept at reset value.
Bits 28:24 PROT[4:0]: bus transfer protection
In the AHB-APs, this field sets the protection attributes HPROT[4:0] of the bus transfer.
XXXX0: Instruction fetch
XXXX1: Data access
XXX0X: User mode
XXX1X: Privileged mode
XX0XX: Non-bufferable
XX1XX: Bufferable
X0XXX: Non-cacheable
X1XXX: Cacheable
0XXXX: Non-exclusive
1XXXX: Exclusive
Bit 23 SPISTATUS: status of SPIDEN option bit (read only)
This signal determines whether the debugger can access secure memory.
0: Secure AHB transfers blocked
1: Secure AHB transfers allowed
Bits 22:12 Reserved, must be kept at reset value.
Bits 11:8 MODE[3:0]: barrier support enabled
Defines if memory barrier operation is supported.
0x0: Not supported
Bit 7 TRINPROG: transfer in progress (read only)
Indicates if a bus transfer is in progress on the AP.
0x0: No transfer in progress
0x1: Bus transfer in progress
Bit 6 DEVICEEN: device enabled (read only)
Defines whether the AP can be accessed.
0x1: AP access enabled
1338/1454
28 27 26 25
PROT[4:0]
r r r r
12 11 10 9
MODE[3:0]
r r r
24 23 22
SPISTA
Res.
TUS
r r
8 7 6
TRINP DEVIC
ADDRINC[1:0]
ROG EEN
r r r
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res.
r r r
RM0453
17 16
Res. Res.
1 0
SIZE[2:0]]
r r