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RM0453
38.6.2
DWT cycle count register (DWT_CYCCNTR)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
r
r
r
15
14
13
r
r
r
Bits 31:0 CYCCNT[31:0]: processor clock cycle counter
38.6.3
DWT CPI count register (DWT_CPICNTR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 CPICNT[7:0]: CPI counter
Counts additional cycles required to execute multi-cycle instructions (except those recorded
by DWT_LSUCNTR) and counts any instruction fetch stalls.
38.6.4
DWT exception count register (DWT_EXCCNTR)
Address offset: 0x00C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
28
27
26
25
r
r
r
r
12
11
10
9
r
r
r
r
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
24
23
22
CYCCNT[31:16]
r
r
r
8
7
6
CYCCNT[15:0]
r
r
r
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
rw
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
rw
rw
RM0453 Rev 2
Debug support (DBG)
21
20
19
18
r
r
r
r
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
5
4
3
2
CPICNT[7:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
EXCCNT[7:0]
rw
rw
rw
rw
17
16
r
r
1
0
r
r
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
rw
rw
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