Processor Machine Check Code - IBM 4381 Manual

Fixed Logout Area Locations 232-239
0-11
16-19
20-31
46-47
Machine Check Storage Validity Validity
Types Error Bits Bits 48-63
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Bit 0 2 3 4 5 6 7 8 9 10 11 12-13 14 15 16 17 1B 19 20-31 32-45 46 47 48
Storage
Bit Interruption Type Bit Error Bit
Valid Fixed Area Data
0
SD-System Damage 15
Delayed (S/370 only) 20-23
Machine Check Old PSW (48-55)
1 PD-Instruction Processing
16 Storage 20AMWP
Damage
Error
21 Masks and Protect Key
2
SR-System Recovery Uncorrected
22 Program Mask and Condition Code
3
TD-Timer Damage (S/370 only) 17 Storage 23 Instruction Address
4 CD-Timing Facilities Damage Error 24
Failing Storage Address (248,249)
5
ED-External Damage (S/370 only)
Corrected
25 Unused
7
DG-Degradation 18 Key in 26
External Damage Code
9
CP-Pending CAW Report
Storage Error 27 Floating Point Registers (352-383)
(370-XA only) Uncorrected 28
General Registers (384-447)
11 CK-Channel Subsystem
19 Storage Degradation
29
Control Registers (448-511)
Damage (370-XA only) 30
Unused
14 B- Backed up 31 Storage (Validity of processor storage
being processed by instructions
when interruption occurred)
46 CPU Timer Value
47 Clock Comparator Value
Figure 16. 4381 Processor machine check code
Repressible Machine Check Interruptions
Repressible machine check interruptions are the following:
• Interval Timer Damage. This interruption can occur if PSW bit 13 and the
external damage mask bit are on to indicate damage to the interval timer in
System/370 mode. The TD bit is stored in the machine check code. An
interval timer is not implemented for System/370-XA mode of operation.
Timing Facilities Damage. This interruption can occur when PSW bit 13 and
the external damage mask (for System/370 mode) or timing facilities damage
mask (for System/370-XA mode) bit are on. It indicates damage to the
time-of-day clock, CPU timer, or clock comparator. The CD bit is stored in
the machine check code. No differentiation among errors in these three timing
facilities is made because of the implementation used. If one facility is failing,
none is usable, since a time-of-day clock and a hardware decrementer are used
to implement the three timing facilities.
An interval timer/timing facilities damage machine check interruption is
generated when the time-of-day clock enters the error state as a result of a
detected malfunction that could have affected the validity of the clock value or
when damage to the interval timer, CPU timer, or clock comparator occurs.
This interruption (with instruction processing damage as well as timer damage
indicated) is also taken when (1) a SET CPU TIMER or STORE CPU TIMER
Section 60: Reliability, Availability, and Serviceability (RAS)
103