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3.3.4
The Time Base
The PowerPC Architecture provides a 64-bit time base. "Time Base" on page 11-2 describes the
architected time base. Access to the time base is through two 32-bit time base registers (TBRs). The
least-significant 32 bits of the time base are read from the Time Base Lower (TBL) register and the
most-significant 32 bits are read from the Time Base Upper (TBU) register.
User-mode access to the time base is read-only, and there is no explicitly privileged read access to
the time base.
The mftb instruction reads from TBL and TBU. Writing the time base is accomplished by moving the
contents of a GPR to a pair of SPRs, which are also called TBL and TBU, using mtspr.
Table 3-5 shows the mnemonics and names of the TBRs.
Table 3-5. Time Base Registers
Mnemonic
Register Name
Access
TBL
Time Base Lower (Read-only)
Read-only
TBU
Time Base Upper (Read-only)
Read-only
3.3.5
Machine State Register (MSR)
The Machine State Register (MSR) controls processor core functions, such as the enabling or
disabling of interrupts and address translation.
The MSR is written from a GPR using the mtmsr instruction. The contents of the MSR can be read
into a GPR using the mfmsr instruction. MSR[EE] is set or cleared using the wrtee or wrteei
instructions.
The MSR contents are automatically saved, altered, and restored by the interrupt-handling
mechanism. See "Machine State Register (MSR)" on page 1 0-28.
CE
PR
ME
DWE
DR
o
Figure
3-9.
Machine State Register (MSR)
0:12
Reserved
13
WE
Wait State Enable
If MSR[WE]
=
1, the processor remains in
o
The processor is not in the wait state.
the wait state until an interrupt is taken, a
1 The processor is in the wait state.
reset occurs, or an external debug tool
clears WE.
14
CE
Critical Interrupt Enable
Controls the critical interrupt input and
o
Critical interrupts are disabled.
watchdog timer first time-out interrupts.
1 Critical interrupts are enabled .
15
...
Reserved
..
Preliminary
Programming Model
3-15
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