Modules - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Modules

17.4 Modules
17.4.1 Sensor Controller
17.4.1.1 Introduction
The sensor controller module is a proprietary, lightweight CPU optimized for low power. Some
architectural highlights include the following:
• Comprehensive 2-operand load and store RISC-style instruction set with high code density
• All instructions consist of one 16-bit opcode
• Eight general-purpose registers of configurable width (up to 16 bits)
• 8-bit immediate instructions embedded in opcode, extendable to 16 bits using a prefix instruction
• Powerful memory-addressing modes
• Efficient manipulation of single bits in I/O space
• Dedicated support for efficient handling of external events
• Vectorized reset and wake-up events allow direct branch to handler address in the vector table
• Multiple power-down features, including clock-stop when waiting for external events and wakeup
• Low-power implementation with explicit power gating
• 2-clock execution for all instructions (3-clock for prefixed instructions)
17.4.1.2 Registers
The sensor controller has eight 16-bit general-purpose registers, R0 to R7. The registers are used as
operands in all data operations, and also for memory and I/O addressing. All integer registers can be used
for any operation, except for a few instructions that require dedicated use of the integer registers R0 or R1
only. The size of a register is known as a word, and all operations operate on entire words; there are no
such concepts as byte, halfwords, and so forth.
Dedicated flag registers implement the traditional zero (Z), negative (N), carry (C), and overflow (V) status
indications. A dedicated loop-count and loop-address register support highly efficient looping instructions.
The program counter (PC) is used to address the instruction memory and the CPU has a built-in 3-level
stack to store the PC during subroutine calls.
Most of the sensor controller registers are memory-mapped and are available for the system CPU to read
or write. These are found in the AUX_SCE:FETCHSTAT and the AUX_SCE:CPUSTAT registers.
17.4.1.3 Interfaces
The sensor controller has the following interfaces:
• Instruction interface towards AUX_RAM
• Data interface towards AUX_RAM
• I/O interface towards the peripheral bus
• Event interface towards the event control module
• Power management interface towards the AUX wake-up controller
The data, I/O, and instruction interfaces are all 16-bit interfaces. The data and instruction interfaces are
time-interleaved, so both can access the AUX_RAM without affecting each other. The CPU automatically
selects the interface based on the instruction being used.
17.4.1.4 Events, Sleep, and Clock Management
The sensor controller has eight events connected to its event inputs, that are used with the wev0 and
wev1 instructions (wait for the event to be 0 or 1). In addition, before executing the sleep instruction, it is
possible to configure four additional events that can wake up the sensor controller again.
These events are used to control program flow upon wakeup and to save power.
1194
AUX – Sensor Controller with Digital and Analog Peripherals
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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