Samsung S5PC110 Manual page 1107

Figure 2-19 Input DMA or External Camera Interface ..................................................................................... 2-20
Figure 2-20 Frame Buffer Control .................................................................................................................... 2-21
Figure 2-21 Camera Window Offset Sheme .................................................................................................... 2-29
Figure 2-22 Interrupt Generation Scheme ....................................................................................................... 2-34
Figure 2-23 Image Mirror and Rotation ............................................................................................................ 2-41
Figure 2-24 YCbCr Plane Memory Storing Style ............................................................................................. 2-45
Figure 2-25 Scaling Scheme ............................................................................................................................ 2-46
Figure 2-26 I/O Timing Diagram for Direct Path............................................................................................... 2-53
Figure 2-27 Input & Output Modes in CAMIF................................................................................................... 2-54
Figure 2-28 Capture Frame Control ................................................................................................................. 2-59
Figure 2-29 Image Effect.................................................................................................................................. 2-62
Figure 2-30 ENVID_M SFR Setting When Input DMA Start to Read Memory Data........................................ 2-69
Figure 2-31 SFR and Operation (Related Each DMA When Selected Input DMA Path) ................................ 2-70
Figure 2-32 Input DMA Address Change Timing (progressive to progressive) ............................................... 2-70
Figure 2-33 Input DMA Address Change Timing (progressive to interlace) .................................................... 2-71
Figure 2-34 Input DMA Address Change Timing (Software Update)............................................................... 2-71
Figure 2-35 Input/Ouput DMA pingpong Address Change Scheme................................................................ 2-72
Figure 2-36 Input DMA Progressive-in to Interlace-out (only interlace_out setting) ........................................ 2-72
Figure 2-37 Input DMA Progressive-in to Interlace-out (Weave_in and Interlace_out setting) ....................... 2-72
Figure 2-38 Input DMA Offset and Image Size ................................................................................................ 2-78
Figure 2-39 Output DMA Offset and Image Size ............................................................................................. 2-78
Figure 3-1 MIPI DSI System Block Diagram ...................................................................................................... 3-2
Figure 3-2 Rx Data Word Alignment .................................................................................................................. 3-4
Figure 3-3 Signal Converting Diagram in Video Mode....................................................................................... 3-5
Figure 3-4 Block Timing Diagram of HSA Mode (HSA mode reset: DSIM_CONFIG[20] = 0)........................... 3-6
Figure 3-5 Block Timing Diagram of HSA Mode (HSA mode set: DSIM_CONFIG[20] = 1) .............................. 3-6
Figure 3-6 Block Timing Diagram of HBP Mode (HBP Mode Reset: DSIM_CONFIG[21] = 0) ......................... 3-7
Figure 3-7 Block Timing Diagram of HBP Mode (HBP Mode Set: DSIM_CONFIG[21] = 1) ............................. 3-7
Figure 3-8 Block Timing Diagram of HFP Mode (HFP Mode Reset: DSIM_CONFIG[22] = 0).......................... 3-7
Figure 3-9 Block Timing Diagram of HFP Mode (HFP Mode Set: DSIM_CONFIG[22] = 1).............................. 3-7
Figure 3-10 Block Timing Diagram of HSE Mode (HSE Mode Reset: DSIM_CONFIG[23] = 0) ......................... 3-8
Figure 3-11 Block Timing Diagram of HSE Mode (HSE Mode Set: DSIM_CONFIG[23] = 1) ............................. 3-8
Figure 3-12 Stable VFP Area Before Command Transfer Allowing Area............................................................ 3-9
Figure 3-13 I80 Interface Timing Diagram ......................................................................................................... 3-10
Figure 3-14 Packetizing for MIPI DSI Command Mode from I80 Interface ....................................................... 3-11
Figure 4-1 MIPI CSI System Block Diagram ...................................................................................................... 4-2
Figure 4-2 Waveform of Output Data ................................................................................................................. 4-3
Figure 4-3 MIPI CSIS Data Alignment ............................................................................................................... 4-4
Figure 5-1 SGX540 Block Diagram.................................................................................................................... 5-5
Figure 5-2 Block Diagram of Integration Information with Related Block ........................................................ 5-10
Figure 6-1 MFC Block Diagram.......................................................................................................................... 6-6
Figure 6-2 Luma and Chroma Pixel (8 bytes-aligned) ....................................................................................... 6-7
Figure 6-3 QCIF Image in 16pixel x 16lines (1x1) Tiled Mode........................................................................... 6-8
Figure 6-4 QCIF Image in 64pixel x 32lines (4x2) Tiled Mode........................................................................... 6-9
Figure 6-5 Shared Memory Input for Decoders ............................................................................................... 6-77
Figure 6-6 Shared Memory Output for Decoders............................................................................................. 6-78
Figure 6-7 VC1 Parameters ............................................................................................................................. 6-79
Figure 6-8 Shared Memory Input for Encoders................................................................................................ 6-80
Figure 6-9 Shared Memory Output for Encoders............................................................................................. 6-80