Mcbsp To St-Bus Block Diagram; Double-Rate St-Bus Clock Example - Texas Instruments TMS320C6000 DSP Reference Manual

Clocking and Framing Examples
• CLK(R/X)M = 1: CLK(R/X)_int generated internally by the sample rate generator
• GSYNC = 1: CLKG is synchronized with the external frame sync signal input on FSR. CLKG is not
synchronized (it runs freely) until the frame sync signal is active. Also, FSR is regenerated internally to
form a minimum pulse width. FPER and FWID are don't cares.
• CLKSM = 0: external clock (CLKS) drives the sample rate generator
• CLKSP = 1: falling edge of CLKS generates CLKG and thus CLK(R/X)_int
• CLKGDV = 1: receive clock (shown as CLKR) is half of CLKS frequency
• FS(R/X)P = 1: active (low) frame sync pulse
• (R/X)FRLEN1 = 11111b: 32 elements per frame
• (R/X)WDLEN1 = 0: 8-bit element
• (R/X)PHASE = 0: single-phase frame and (R/X)FRLEN2 = (R/X)WDLEN2 = X
• (R/X)DATDLY = 0: no data delay
• FRST = 1: frame-sync generator is out of reset and is able to generate frame-sync signal (FSG) to be
used by transmit and receive sections
• FSRM = 1: receive frame-sync signal is driven internally by the sample-rate generator frame-sync
signal (FSG)
• FSGM = 1: transmit frame-sync signal is driven by the sample-rate generator frame-sync signal (FSG)
• FSXM = 1: transmitter uses internally-generated frame-sync signal and is available at the FSX pin
Note: The FSX and FSR pins should not be connected together.
4.096-MHz CLKS
FSR external
FSG, FSR_int,
FSX_int
2.048-MHz CLKG,
CLKR_int, CLKX_int
(first FSR)
DR, DX (first FSR)
CLKG, CLKR_int,
CLKX_int
(subsequent FSR)
DR, DX
(subsequent FSR)
36 Clocks, Frames, and Data
Figure 4-15. McBSP to ST-BUS Block Diagram
ST-BUS
STo
STi
Fo
C4
Figure 4-16. Double-Rate ST-BUS Clock Example
Sample point
E1B7 E1B6 E1B5
E32B0 E1B7 E1B6 E1B5
McBSP
DR
DX
FSR
CLKS
E1B4 E1B3 E1B2 E1B1
E1B4
E1B3 E1B2 E1B1
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E1B0 E2B7
E1B0 E2B7
SPRU580E – December 2005