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4 Functional Block Diagram
(1.8 V to 3.8 V) VDSS_PU
User DIO_0-31
(1.8 V to 3.8 V) VDSS
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48-MHz
Crystal
JTAG
RESET_N
CC1312P
GND
DCDC
Passives
Figure 4-1. CC1312PSIP Block Diagram
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32.768-kHz
Crystal
+20-dBm
IPC
DIO_3
DIO_0
+14-dBm/RX
IPC
CC1312PSIP
CC1312PSIP
SWRS293 – NOVEMBER 2023
RF
RF (50 Ω)
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